The present invention relates to a method for manufacturing a semiconductor device, and also relates to the semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device having wires formed by a dual damascene process, and also relates to the semiconductor device.
As a process for forming wires of a semiconductor device, there has been a via-first dual damascene process that involves a low-k interlayer dielectric (a low dielectric constant film (a low-k film)). In this dual damascene process, a single damascene wire is formed on an insulating film, with a barrier metal being interposed between the single damascene wire and the insulating film. The low-k film such as a SiOC composition film is formed on the single damascene wire. A via hole is formed in the low-k film on the single damascene wire, and a wire groove is formed on the via hole. A wiring metal material is then provided to fill the via hole and the wire groove via a barrier metal. In the process of forming the via hole, the low-k film is etched by a resist processing technique and the reactive ion etching (RIE) technique, and the resist is removed by the Asher technique.
During the RIE process, however, the surface of the low-k film is exposed to a plasma atmosphere. As a result, the carbon (C), the methyl group (CH3), or the aryl group (CH substituent) in the low-k film are desorbed, and a SiO film is formed on the surface of the etched low-k film. Exposed to the air, the SiO film absorbs moisture to form a damaged layer (a SiOH layer) on the surface of the etched low-k film. The barrier metal reacts with the OH group in the damaged layer, to form an oxide film on the surface of the barrier metal. The oxide film lowers the reliability of the wires. During the Asher process, a damaged layer is also formed.
In a case where the damaged layer is removed by wet etching with the use of a chemical solution containing a HF-based substance, the low-k film is deformed by the amount corresponding to the removed damaged layer. As a result, a width of the trench (particularly, the via diameter) becomes greater, and hinders miniaturization of the semiconductor device.
As described above, by the conventional semiconductor device manufacturing process, it is difficult to increase a reliability of the wire and prevent an increase in a width of the trench during the dual damascene process (Japanese Patent Application Laid-Open No. 2006-5010).